The present invention relates generally to integrated circuits and, more particularly, to a method and system for clocking integrated circuits.
Integrated circuits (IC), such as those implemented on a single silicon substrate and often known as a system-on-chip (SoC), have large numbers of digital components, each or which consumes power. So called dynamic IR-drop is a problem for integrated circuits and results from high peak power consumption by the IC. Dynamic IR-drop may also be known as peak-power IR drop. The dynamic IR-drop can impact the IC's functionality and reliability. Furthermore, high peak current or power can create electromagnetic interference (EMI) issues.
In an IC, each digital component or module is operated in response to a clock signal. FIG. 1A illustrates power consumption for a digital buffer responsive to a clock signal transitioning between a low logic value (0) and a high logic value (1). FIG. 1B illustrates power consumption for a digital system comprising a plurality of digital components in which power consumption is approximately nine times that for the single digital component shown in FIG. 1A. The increase in power consumption is caused by a plurality of the digital components being simultaneously clocked (barring small clock signals delays within the system), which leads to a general overlap of peak power consumption associated with each digital component.
Given that peak power consumption is an issue for ICs, it would be advantageous to be able to reduce peak power consumption in ICs.